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mb86064 copyright ? 2004-2005 fujitsu microelectronics europe gmbh production page 1 of 52 disclaimer : the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales repr esentatives before ordering.the information and circuit diagrams in this document are presented ?as is?, no license is grant ed by implication or otherwise. datasheet october 2005 version 1.2 fme/ms/dac80/ds/4972 dual 14-bit 1gsa/s dac the fujitsu mb86064 is a dual 14-bit 1gsa/s digital to analog converter (dac), delivering exceptional dynamic performance. each high performance dac core is capable of generating multi-standard, multi-carrier communication transmit signals, suitable for 2, 2.5 and 3g systems. dac data is input via two high-speed lvds ports. these operate in a pseudo double data rate (ddr) mode, with data latched on both rising and falling edges of the clock. alternatively, the device can be configured as a multiplexed dual-port single dac. to simplify system integration the dac operates from a clock running at half the dac conversion rate. features dual 14-bit, 1gsa/s digital to analog conversion exceptional dynamic performance 74dbc aclr for 4 umts carriers @ 276mhz direct-if 100mhz image-free generated bandwidth capability supports umts plus digital pre-distortion bandwidth proprietary performance enhancement features lvds data interface register selectable on-chip lvds termination resistors fujitsu 4-wire serial control interface two 16k point programmable on-chip waveform memories low power 3.3v analog and 1.8v digital operation 750mw single dac operation power dissipation at 1gsa/s 0.18m cmos technology with triple well performance enhanced efbga package industrial temperature range operation (-40c to +85c) applications multi-carrier, multi-standard cellular infrastructure cdma, w-cdma, gsm/edge, umts wideband communications systems high direct-if architectures arbitrary waveform generation test equipment radar, video & display systems plastic package efbga-120 package dimensions 12 mm x 12 mm pin assignment e3 e1 f4 f2 g3 g1 h4 h2 j3 j1 k4 k2 l3 l1 m4 m2 n3 n1 p4 p2 r3 r1 t4 t2 u3 v2 w3 w1 aa5 ac5 y6 ab6 aa7 ac7 y8 ab8 aa9 ac9 y10 ab10 aa11 ac11 y12 ab12 aa13 ac13 y14 ab14 aa15 ac15 y16 ab16 aa17 ac17 y18 ab18 aa19 ac19 w21 w23 v20 v22 u21 u23 t20 t22 r21 r23 p20 p22 n21 n23 m20 m22 l21 l23 k20 k22 j21 j23 h20 h22 g21 g23 f20 f22 e21 e23 c19 a19 d18 b18 c17 a17 b16 d16 a15 c15 b14 d14 a13 c13 b12 d12 a11 c11 b10 d10 a9 c9 b8 a7 c7 d8 b6 d6 a5 c5 index n10 n12 n14 r10 r12 r14 l10 l12 l14 j10 j12 j14 k9 k11 k13 k15 m9 m11 m13 m15 p9 p11 p13 p15 serial_in serial_en avss ioutb_b iout_b avd33 bgap avd18_clk avd25 avd33 iout_a ioutb_a avss dac_scan spare clkin clkinb vlow_a avd18_a avd18_a x_reset test vlow_b x_a10 vref rref avss serial_out serial_clk avd18_b avd18_b a10 dvss dvdd dvdd dvss a8 a6 x_a8 x_a6 a2 x_a2 a4 dvdd x_b9 dvss x_a4 b9 x_b10 b10 dvdd dvss dvdd dvss dvdd dvss x_a3 a3 a1 nc x_a1 dvss nc a5 x_a5 a7 x_a7 dvdd a9 x_a9 b13 x_b13 dvss lpclk_out a13 x_lpclk_in lpclk_in x_lpclk_out x_a13 dvss x_a11 a11 clk1_out a14 dvdd x_a12 x_clk1_out x_a14 a12 b11 dvss x_b14 x_clk2_out clk2_out dvdd x_b12 dvdd b14 b12 x_b11 b6 x_b6 b8 x_b8 b2 x_b2 x_b3 b1 b3 dvdd x_b4 b5 nc x_b1 dvss b4 x_b5 b7 x_b7 nc u1 v4 not to scale. viewed from above. all centre pins : tg
october 2005 version 1.2 fme/ms/dac80/ds/4972 mb86064 dual 14-bit 1gsa/s dac page 2 of 52 production copyright ? 2004-2005 fujitsu microelectronics europe gmbh disclaimer : the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales repr esentatives before ordering.the information and circuit diagrams in this document are presented ?as is?, no license is grant ed by implication or otherwise. contents 1 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.1 clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.1.1 input clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.1.2 dac core clocks programmable delays . . . . . . . . . . . . . . . 5 1.1.3 waveform memory module clock programmable delay . . . 6 1.1.4 clock outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.1.5 loop clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.2 dac data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.2.1 data from the lvds interface. . . . . . . . . . . . . . . . . . . . . . . 11 1.2.2 adjusting the input data timing . . . . . . . . . . . . . . . . . . . . . 12 1.2.3 data from the waveform memory module . . . . . . . . . . . . . 13 1.3 dac core current references . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1.4 voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 1.5 analog output reference resistor . . . . . . . . . . . . . . . . . . . . . . . . . 14 1.6 analog outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 1.6.1 frequency planning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 1.7 reset and power down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2 serial control interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.1 programming a read/write cycle . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3 waveform memory module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.1 dual port, interleaved lvds data via the wmm . . . . . . . . . . . . . . . 22 3.2 waveform memory module operation. . . . . . . . . . . . . . . . . . . . . . . 23 3.2.1 waveform memory access via the serial interface . . . . . . 24 3.2.2 writing data into the memories. . . . . . . . . . . . . . . . . . . . . . 26 3.3 software reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.2 digital interface specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.3 dc specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.4 ac specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4.5 dynamic performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.6 clock specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 4.7 serial interface timing specifications . . . . . . . . . . . . . . . . . . . . . . . 33 4.8 power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5.1 pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5.2 pin definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 5.3 package data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
october 2005 version 1.2 fme/ms/dac80/ds/4972 mb86064 dual 14-bit 1gsa/s dac copyright ? 2004-2005 fujitsu microelectronics europe gmbh production page 3 of 52 disclaimer : the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales repr esentatives before ordering.the information and circuit diagrams in this document are presented ?as is?, no license is grant ed by implication or otherwise. 5.4 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 6 application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 6.1 pcb power & ground plane splits and decoupling . . . . . . . . . . . . 40 6.2 input clock interfacing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 6.3 clock duty cycle optimisation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 6.4 analog output interfacing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 6.4.1 transformer coupled output circuit. . . . . . . . . . . . . . . . . . 44 6.4.2 direct interface to quadrature modulator . . . . . . . . . . . . . . 45 6.5 example setup register settings . . . . . . . . . . . . . . . . . . . . . . . . . . 46 6.5.1 dual dac, lvds data, clock outputs enabled . . . . . . . . . 46 6.5.2 single dac, lvds data port a, driving dac a . . . . . . . . . 46 6.5.3 multiplexed lvds data into dac a (a=even, b=odd) . . 46 6.5.4 waveform memory module, different a & b waveforms . . 46 6.6 technical support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 7 development kit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 7.1 using dkusb-1 in target applications. . . . . . . . . . . . . . . . . . . . . . 49 appendix a default register settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 a.1 dac core registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 a.2 waveform memory module registers . . . . . . . . . . . . . . 51 caution electrostatic discharge sensitive device high electrostatic charges can accumulate in the human body and discharge without detection. ensure proper esd procedures are followed when handling this device. this device contains circuitry to protect the inputs against damage due to high static voltages or electric fields. however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit.
october 2005 version 1.2 fme/ms/dac80/ds/4972 mb86064 dual 14-bit 1gsa/s dac page 4 of 52 production copyright ? 2004-2005 fujitsu microelectronics europe gmbh disclaimer : the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales repr esentatives before ordering.the information and circuit diagrams in this document are presented ?as is?, no license is grant ed by implication or otherwise. 1 functional description the mb86064 is a high performance dual 14-bit 1gsa/s dac. in addition to two dac cores the device features a host of features designed to help both system integration and operation. a functional block diagram is shown in figure 1. figure 1 mb86064 functional block diagram the device features a number of proprietary performance enhancement features. for example, analog performance at high frequencies is enhanced by novel current switch and switch driver designs which provide constant data-independent switching delay, reducing jitter and distortion. each dac core can be regarded as two interleaved dacs running at half rate. the main reason for adopting this approach is that the switch driver inherently includes a multiplex function through its two input ports. compared to a conventional switch driver this allows twice as long to acquire and convert, though because the two paths share current sources they match exactly at low frequencies. in terms of input data, this approach allows easy interfacing to ddr data generating devices. also integrated into the device is a comprehensive waveform memory module (wmm). waveforms can be downloaded, via the serial control interface, to drive the dac cores in the absence of a suitable external data generator. port a data input 14-bit lvds port b data input 14-bit lvds waveform memory a (16k points) waveform memory a (16k points) waveform memory module waveform memory b (16k points) waveform memory b (16k points) rf clock input e.g. 500mhz loop clock input lvds loop clock output lvds clock output 2 lvds clock output 1 lvds 4-wire serial control interface control interface 1.8v lvcmos analog output a analog output b efbga-120 1, 2, 4, 8 dac a (14-bit) dac b (14-bit) 1, 2, 4, 8 double-edge clocked (1gsa/s)
october 2005 version 1.2 fme/ms/dac80/ds/4972 mb86064 dual 14-bit 1gsa/s dac copyright ? 2004-2005 fujitsu microelectronics europe gmbh production page 5 of 52 disclaimer : the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales repr esentatives before ordering.the information and circuit diagrams in this document are presented ?as is?, no license is grant ed by implication or otherwise. 1.1 clock the device requires an input clock at half the dac conversion rate, with sufficient spectral purity to not impact the target analog output performance. the dac cores are clocked on both rising and falling edges of the input clock. this forms an effect of two interleaved converters in each dac core. a characteristic of this architecture is a suppressed image of the generated signal, appearing reflected about fs(dac)/4 = (fclk-fsig). any duty cycle error in the input clock will exacerbate this image. this can be minimised by trimming the differential dc offset at the clock input pins. 1.1.1 input clock the input clock should be applied to the mb86064 through input pins clkin and clkinb. the device is designed to accept a differential sinusoidal clock. once on chip and converted to cmos the clock is distributed to a number of blocks throughout the device. the dac cores are supplied directly from the input clock buffer to ensure minimal degradation to the clock?s purity. figure 2 clock distribution 1.1.2 dac core clocks programmable delays the dac core clocks contain programmable delays. these allow adjustment to the point at which data is clocked into the dac core and when the analog portion of the dac subsequently latches the clock input rf wmm_clk_dly 0x1c1 - pg6 clkout1_clk_dly 0x1c1 - pg7 clock output 1 lvds clock output 2 lvds n clkout2_cfg 0x00 - pg7 clkout1_cfg 0x00 - pg7 2 4 8 x_reset clocks to dac cores loop clock input lvds loop clock output lvds en_int_term 0x1c4 - pg11 waveform memory module clock to waveform memory module dac_clk_dly 0x1b2 - pg6 dac_latch_dly 0x1b2 - pg6 pdn_outcks 0x1c3 - pg16 en_ref_clk 0x1c4 - pg7 en_wmm_clk 0x1c4 ? pg21 loop_clk_dly 0x1c1 - pg9 en_int_term 0x1c4 - pg11 en_int_term 0x1c4 - pg11 clkout2_clk_dly 0x1c1 - pg8
october 2005 version 1.2 fme/ms/dac80/ds/4972 mb86064 dual 14-bit 1gsa/s dac page 6 of 52 production copyright ? 2004-2005 fujitsu microelectronics europe gmbh disclaimer : the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales repr esentatives before ordering.the information and circuit diagrams in this document are presented ?as is?, no license is grant ed by implication or otherwise. data. the delay settings are programmed through register dac core clock delays, bits dac_clk_dly and dac_latch_dly . based on detailed evaluation by fujitsu these registers should be programmed in accordance with the recommendations given in table 1. note: bold type indicates default setting. see appendix a. 1.1.3 waveform memory module clock programmable delay a programmable delay stage is provided in the clock path prior to being applied to the waveform memory module. this delay stage is programmed through register system clock delays, bits wmm_clk_dly . see table 2. table 1: dac core register: dac core clock delays [0x1b2] label reg bits dac core digital clock delay (0 - 1.5ns, 100ps steps) 3210 dac_clk_dly 0 0 0 0 minimum (* recommended *) :::: 0 1 0 0 medium (default) :::: 1 1 1 1 maximum label reg bits dac core analog latch clock delay (0 - 1.5ns, 100ps steps) 7654 dac_latch_dly 0 0 0 0 minimum (* recommended *) :::: 0 1 0 0 medium (default) :::: 1 1 1 1 maximum table 2: dac core register: system clock delays [0x1c1] (part 1 of 4) label reg bits waveform memory module clock delay (0 - 1.5ns, 100ps steps) 15 14 13 12 wmm_clk_dly 0 0 0 0 minimum (default & recommended) :::: 1 1 1 1 maximum
october 2005 version 1.2 fme/ms/dac80/ds/4972 mb86064 dual 14-bit 1gsa/s dac copyright ? 2004-2005 fujitsu microelectronics europe gmbh production page 7 of 52 disclaimer : the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales repr esentatives before ordering.the information and circuit diagrams in this document are presented ?as is?, no license is grant ed by implication or otherwise. 1.1.4 clock outputs two clock outputs, clk1_out and clk2_out, are provided to enable synchronisation of data generating devices to the dac. the reference clock used by the clock output block can be disabled if required. see table 3. the output frequency can be individually selected as the input clock divided-by-1, 2, 4 or 8. configuration is through register wmm config, bits clkout1_cfg and clkout2_cfg . see table 4. also, programmable delay stages are provided in both clk1_out and clk2_out outputs. these clock output delays are programmed through register system clock delays clkout1_clk_dly and clkout2_clk_dly . see table 5 and table 6. table 3: dac core register: system misc [0x1c4] (part 1 of 3) system misc (bit) label function 0en_ref_clk reference clock control 0 = enabled (default) , 1 = disabled table 4: waveform memory module register: wmm config [0x00] (part 1 of 2) label reg bits divided clock output configuration 3210 clkout1_cfg 0 0 clock output 1 = clock input (default) 0 1 clock output 1 = clock input divided by 2 1 0 clock output 1 = clock input divided by 4 1 1 clock output 1 = clock input divided by 8 clkout2_cfg 0 0 clock output 2 = clock input (default) 0 1 clock output 2 = clock input divided by 2 1 0 clock output 2 = clock input divided by 4 1 1 clock output 2 = clock input divided by 8 table 5: dac core register: system clock delays [0x1c1] (part 2 of 4) label reg bits clock output delay (0 - 1.5ns, 100ps steps) 7654 clkout1_clk_dly 0000minimum (default) :::: 1111maximum
october 2005 version 1.2 fme/ms/dac80/ds/4972 mb86064 dual 14-bit 1gsa/s dac page 8 of 52 production copyright ? 2004-2005 fujitsu microelectronics europe gmbh disclaimer : the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales repr esentatives before ordering.the information and circuit diagrams in this document are presented ?as is?, no license is grant ed by implication or otherwise. the clock outputs are designed to drive a doubly-terminated lvds line (7ma drive into a bridged 50 ? load) for the best possible signal integrity. 100 ? termination resistors should be connected across the q and q signals at each end of the differential line. enabling the internal lvds terminations provides the required source termination on-chip. 1.1.5 loop clock maintaining valid clock-to-data timing becomes increasingly difficult at higher clock rates, particularly over tolerance with device-to-device variations. the mb86064 minimises potential problems through its ddr data interface and by providing a unique loop-clock facility. figure 3 loop clock implementation the on-chip ?loop? consists of an lvds input buffer connected to an lvds output buffer through a programmable delay stage. this loop-through, and the associated tracking from/to the data table 6: dac core register: system clock delays [0x1c1] (part 3 of 4) label reg bits clock output delay (0 - 1.5ns, 100ps steps) 3210 clkout2_clk_dly 0 0 0 0 minimum (default) :::: 1 1 1 1 maximum clock (500 mhz) dll/ pll reference clock feedback clock clock x2 (1ghz) dac fujitsu mb86064 dac lvds i/o clock 2 (500mhz) increase delay to ?retard? data increase delay to ?advance? data fpga
october 2005 version 1.2 fme/ms/dac80/ds/4972 mb86064 dual 14-bit 1gsa/s dac copyright ? 2004-2005 fujitsu microelectronics europe gmbh production page 9 of 52 disclaimer : the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales repr esentatives before ordering.the information and circuit diagrams in this document are presented ?as is?, no license is grant ed by implication or otherwise. generating device, can be incorporated in the feedback loop of a delay-locked loop (dll) or phase- locked loop (pll) clock generator, within the generating device. this enables the system to compensate for variations in input/output (i/o) and propagation delays in both the data generating device and the dac. pcb and/or cable propagation delays within the loop are also compensated for but these are not expected to exhibit significant variation between systems. it is the i/o & on-chip delays that will dominate. it is important to make sure that the clock output frequency is within the specification of the dll/pll. if it is too high an appropriate divided clock output should be programmed as detailed in table 7. with the loop clock implemented as illustrated in figure 3, increasing the clock output delay delays the data arriving at the dac relative to the dac input clock. by contrast increasing the loop clock delay, within the feedback loop of the dll/pll, advances the relative timing. it is important not to adjust both delays simultaneously else they will counteract each other. either the clock output delay or the loop clock delay, or both, should be zero. connections to the loop clock are via pins lpclk_in and lpclk_out. the loop clock delay is programmed through register system clock delays, loop_clk_dly . see table 7. with the dac core clock delays set to their recommended values (0x00), monitoring the analog output for a valid signal while adjusting the clock output and loop clock delays enables a diagram of valid & invalid data latching points to be produced. an example is illustrated in figure 4. figure 4 finding valid data eyes using loop clock table 7: dac core register: system clock delays [0x1c1] (part 4 of 4) label reg bits loop clock delay (0 - 1.5ns, 100ps steps) 11 10 9 8 loop_clk_dly 0000minimum (default) :::: 1111maximum system clock delays register [0x1c1] retard bits [7:4] or [3:0] (0 - 1.5ns) advance bits [11:8] (0 - 1.5ns) dac core -1.5ns 0 + 1.5ns clock 00 delays [0x1b2]
october 2005 version 1.2 fme/ms/dac80/ds/4972 mb86064 dual 14-bit 1gsa/s dac page 10 of 52 production copyright ? 2004-2005 fujitsu microelectronics europe gmbh disclaimer : the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales repr esentatives before ordering.the information and circuit diagrams in this document are presented ?as is?, no license is grant ed by implication or otherwise. this example used an altera stratix fpga evaluation platform driving a fujitsu development kit at 800msa/s. another circuit implementation would exhibit different absolute timings but similar relative adjustments. having evaluated a prototype design and final loop clock delay settings chosen, the real benefit of using the loop clock facility is in maintaining valid clock-to-data timing at these settings. figure 5 illustrates this in operation by using excessive variation in supply voltages to emulate both fast and slow fpga and dac components being used together in production. figure 5 maintaining valid clock-to-data timing using look clock no loop-clock w ith loop-clock low typ. high low typ. high 00 0x1c1 = 0x040 11 22 33 44 55 66 77 88 99 aa bb cc dd ee ff fpga 1.4v 1.5v 1.6v 1.4v 1.5v 1.6v 3.1v 3.3v 3.5v 3.1v 3.3v 3.5v dac 1.6v 1.8v 2.0v 1.6v 1.8v 2.0v 2.9v 3.3v 3.6v 2.9v 3.3v 3.6v
october 2005 version 1.2 fme/ms/dac80/ds/4972 mb86064 dual 14-bit 1gsa/s dac copyright ? 2004-2005 fujitsu microelectronics europe gmbh production page 11 of 52 disclaimer : the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales repr esentatives before ordering.the information and circuit diagrams in this document are presented ?as is?, no license is grant ed by implication or otherwise. 1.2 dac data each dac core can be considered as two identical halves, referred to as odd and even. even samples are latched on the falling edge of clock output, whilst odd samples are latched on the rising edge. data should be presented to the dac cores as unsigned binary, 14-bit data. bit 14 is the msb, and bit 1 is the lsb. figure 6 odd and even data sampling data can be supplied to the dac cores either externally via the lvds data bus or internally from the waveform memory module. 1.2.1 data from the lvds interface external data is input to the mb86064 through lvds data ports a (pins a[14:1]) and b (pins b[14:1]). on-chip 100 ? termination resistors are provided to reduce the external component count, selectable through register system misc en_int_term . see table 8 on page 11. the data may be routed to the dac cores through a number of paths. the most direct path routes data straight from the lvds input buffers to the dac core input latches. this is the default configuration, with the dac input multiplexers set to accept data from the lvds inputs according to register wmm config, data_direct . see table 9 below. the dac exhibits a pipeline delay through the device of 18 input clock edges. table 8: dac core register: system misc [0x1c4] (part 2 of 3) system misc (bit) label function 7 en_int_term internal 100r lvds termination enable (all lvds data inputs, loop clock input, loop clock output and reference clock outputs) 0 = disabled, 1 = termination enabled (default) clock output data (port a) data (port b) d n=1 d n+1 d n+3 d n+2 d n+4 d n+5 d n=1 d n+1 d n+2 d n+3 d n+4 d n+5 odd odd odd even even even
october 2005 version 1.2 fme/ms/dac80/ds/4972 mb86064 dual 14-bit 1gsa/s dac page 12 of 52 production copyright ? 2004-2005 fujitsu microelectronics europe gmbh disclaimer : the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales repr esentatives before ordering.the information and circuit diagrams in this document are presented ?as is?, no license is grant ed by implication or otherwise. figure 7 direct data routing from the lvds interface 1.2.2 adjusting the input data timing when using the clock outputs to synchronise the data generator it is possible to adjust the relative input data timing through dac core register system clock delays [7:4] & [3:0], clkout1_clk_dly & clkout2_clk_dly . see table 5 and table 6. increasing this setting delays the arrival of input data. table 9: waveform memory module register: wmm config [0x00] (part 2 of 2) wmm config (bit) label function 4 data_direct dac a and dac b data source 0 = lvds data directly (default) , 1 = waveform memory module data_direct = ?0? (default) 0x00 - pg12 port a data input 14-bit lvds port b data input 14-bit lvds en_int_term 0x1c4 - pg11 en_int_term 0x1c4 - pg11 even even odd odd waveform memory module dac a (14-bit) dac b (14-bit)
october 2005 version 1.2 fme/ms/dac80/ds/4972 mb86064 dual 14-bit 1gsa/s dac copyright ? 2004-2005 fujitsu microelectronics europe gmbh production page 13 of 52 disclaimer : the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales repr esentatives before ordering.the information and circuit diagrams in this document are presented ?as is?, no license is grant ed by implication or otherwise. when using the loop clock, the delay set by loop_clk_dly (table 7) opposes this and effectively advances the input data relative to the reference clock edge. together these adjustments provide approximately 3ns trim range for clock-to-data timing, in 100ps steps. figure 8 lvds input data timing for further details refer to sections 1.1.4 and 1.1.5. 1.2.3 data from the waveform memory module data routing within the waveform memory module is flexible enough to allow a and b data to be interleaved onto a single dac core. however, primarily the waveform memory module is intended to be loaded with waveforms and subsequently read back to drive the dac cores. a complete description of how to use the waveform memory module is given in section 3. 1.3 dac core current references internal current references are required to be configured according to which dac core(s) are enabled. these are controlled by the dac core register dac config. -0.4ns lvds data timing clock input +0.6ns -0.6ns +0.9ns -0.9ns +1.4ns -0.4ns +1.4ns fast slow typical over process tolerances device-to-device comparison due to process variations
october 2005 version 1.2 fme/ms/dac80/ds/4972 mb86064 dual 14-bit 1gsa/s dac page 14 of 52 production copyright ? 2004-2005 fujitsu microelectronics europe gmbh disclaimer : the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales repr esentatives before ordering.the information and circuit diagrams in this document are presented ?as is?, no license is grant ed by implication or otherwise. the appropriate setting of these bits is dependent on the power-down status of the dac cores, determined by register power down [0x1c3] bits pdn_daca and pdn_dacb . 1.4 voltage reference a 1.2v bandgap reference is provided on-chip, although this is left unconnected when an external reference is to be used. to use the internal bandgap reference, pins bgap and vref should be linked via a 1k ? resistor. vref should be decoupled to avss with a 100nf capacitor. for maximum absolute accuracy an external voltage reference should be used. this should be connected to vref through a 1k ? resistor and decoupled as described above. the external voltage reference should be powered from the avd25 pin, which is a regulated 2.5v output with high power supply noise rejection. 1.5 analog output reference resistor from the voltage reference the full scale analog output current is defined by an external reference resistor, r ref , where, e.g. with vref = 1.20v, to give a 20ma full scale output, rref = 960 ? . designs that for simplicity use a 1k ? resistor will result in a marginally lower full scale output current of 19.2ma (-0.35db) unless using an external reference to provide a higher voltage of 1.25v. 1.6 analog outputs the dac outputs are differential current type. a termination resistor, or load, should be used appropriate for the recommended output swing. each dac may be individually powered down. table 10: dac core register: dac config [0x1c0] dac config (bits) configuration 10 x x with dac a and dac b disabled 1 x with dac a enabled, dac b disabled x 1 with dac a disabled, dac b enabled 00 with dac a and dac b enabled (default) bgap mb86064 avss 1k vref 100nf r ref 16 v ref i op --------------------- rref mb86064 avss
october 2005 version 1.2 fme/ms/dac80/ds/4972 mb86064 dual 14-bit 1gsa/s dac copyright ? 2004-2005 fujitsu microelectronics europe gmbh production page 15 of 52 disclaimer : the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales repr esentatives before ordering.the information and circuit diagrams in this document are presented ?as is?, no license is grant ed by implication or otherwise. analog output performance benefits from the chosen dac core architecture, identified in section 1 as similar to two interleaved dacs running at half rate. the big advantage of this approach compared to a single dac running at half the rate is much reduced sinx/x roll-off which gives increased output power and better in-band flatness when generating high output frequencies (e.g. 200mhz and above). this is illustrated in figure 9 as line 1. an alternative approach using a return-to-zero output stage admittedly has the same sinx/x roll off (and switch driver speed) but 6db lower output power and a large image at fclk-fout. see line 2. for reference, line 3 illustrates a conventional dac running at half rate. another aspect of this comparison which should not be overlooked concerns noise performance, increasingly quoted in units of dbm/hz. in terms of snr there is some 7dbs of degradation to consider when comparing a 300mhz test for a standard 400msa/s dac with the mb86064 running at 800msa/s. this is relevant to the noise floor figures quoted in section 4.5 dynamic performance. figure 9 benefits of dac core architecture to sinx/x response 1.6.1 frequency planning systems that require superior dynamic performance should not ignore the dac from the task of frequency planning. to do so could result in impractical specifications or at worst increase the cost and power of the converter that would need to be selected. the mb86064 is designed to deliver the very best dynamic performance across wide bandwidths, as required for communications systems and in particular for multi-carrier applications. preferred generating bands can be demonstrated as those centred at 0.2, 0.3 and 0.4 fdac. in addition, while allowing certain images in-band though at levels unlikely to impact on performance other possible centre frequencies are 0.125 and 0.375 fdac. it is important to remember that conventional dacs running at half the rate or those incorporating a return-to-zero output stage are subject to exactly the same frequency planning constraints as these are defined by nyquist?s theorem. however, a key advantage of the mb86064 is its ability to generate wide bandwidth signals in the 2nd nyquist zone where conventional dacs will be prevented from doing so due to sinx/x attenuation. 0 dbfs frequency -6 target high direct-if generating region
october 2005 version 1.2 fme/ms/dac80/ds/4972 mb86064 dual 14-bit 1gsa/s dac page 16 of 52 production copyright ? 2004-2005 fujitsu microelectronics europe gmbh disclaimer : the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales repr esentatives before ordering.the information and circuit diagrams in this document are presented ?as is?, no license is grant ed by implication or otherwise. 1.7 reset and power down pin x_reset is the device reset pin. on the falling edge of x_reset the device is reset and all registers are set to their default values. after a reset most parts of the device are powered down. see table 11, dac core register power down. power to each internal block may be individually controlled through this register. the dac control register bits, pdn_daca & pdn_dacb , must be set in conjunction with the dac config register bits to ensure the correct internal reference current is used. see section 1.3. examples of typical settings are: 0x0000b80 dac a enabled for lvds data 0x0001580 dac b enabled for lvds data 0x0000180 both dacs enabled for lvds data all are based on both the divided clock outputs and loop-clocks being enabled. table 11: dac core register: power down [0x1c3] power down (bit) label function 0 pdn_reglo low voltage (~1.1v) regulator control 0 = enabled (default) , 1 = powered down 1 pdn_regck 1.8v clock regulator control 0 = enabled (default) , 1 = powered down 2 pdn_reg18 1.8v dac regulator control 0 = enabled (default) , 1 = powered down 3 pdn_reg25 2.5v bandgap regulator control 0 = enabled (default) , 1 = powered down 4 pdn_ckandrefs dac common circuit (clocks, references and bias) control 0 = all enabled (default) , 1 = all powered down 5 pdn_outcks divided output clocks 0 = enabled (default) , 1 = powered down 6 pdn_loopcks loop clocks 0 = enabled, 1 = powered down (default) 7 pdn_odatb access to test output pin by dac b 0 = enabled, 1 = disabled (default) 8 pdn_odata access to test output pin by dac a 0 = enabled, 1 = disabled (default) 9 pdn_indatb dac b data input power down control 0 = enabled, 1 = powered down (default) 10 pdn_indata dac a data input power down control 0 = enabled, 1 = powered down (default) 11 pdn_dacb dac b control n.b. see note below 0 = enabled, 1 = powered down (default) 12 pdn_daca dac a control n.b. see note below 0 = enabled, 1 = powered down (default)
october 2005 version 1.2 fme/ms/dac80/ds/4972 mb86064 dual 14-bit 1gsa/s dac copyright ? 2004-2005 fujitsu microelectronics europe gmbh production page 17 of 52 disclaimer : the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales repr esentatives before ordering.the information and circuit diagrams in this document are presented ?as is?, no license is grant ed by implication or otherwise. 2 serial control interface a simple 4-wire serial control interface is used to control the mb86064. the serial interface uses pins serial_in, serial_out, serial_clk and serial_en. programmed settings are stored in a number of registers which are individually accessible using either an 7-bit (wmm registers) or 10-bit (dac core registers) address/control word. data may be written to or read from each of these registers. the serial interface uses 1.8v lv-cmos logic levels. 2.1 programming a read/write cycle to perform a read or write cycle serial_en should be taken high on the falling edge of serial_clk. this will indicate the start of a frame when latched on the next rising edge. at the same time serial_in should be driven, msb first, with the address of the register to be accessed. data is latched into the device on each rising edge of serial_clk. the register address should be followed with the read/write instruction bit. for a read cycle this bit is ?0?, for a write cycle this bit is ?1?. the device is now ready to transfer data in or out of the addressed register. if the selected register is to be written to, the data should be presented to serial_in, msb first. the data packet only needs to be as long as the register that is being written to, with the lsb presented in the final time slot. if the data source has a fixed length packet size, longer than the register, the data packet should be zero-filled at the msb end. once the data has been transferred into the register, serial_en should be taken low on the falling edge of serial_clk to indicate the end of the read/write cycle and frame. during a write cycle, as data is loaded into the selected register, the previous contents are output on serial_out, msb first. if the selected register is being read, data will be output on serial_out, msb first, nominally coincident with the falling edge of serial_clk. once the register has been read additional clock cycles will produce zero-filled bits until the read cycle is terminated. a read cycle may be terminated by taking the serial_en low on the falling edge of serial_clk. all waveform memory module registers, apart from wmm [even/odd] ram data, read back as eight bit long registers. all other registers will read back at their true length. figure 10 and figure 11 show the write and read cycles (as functional timing diagrams) in more detail. in designs where serial_clk is halted after a write operation, at least three additional clock cycles should be allowed after serial_en has return low. this is necessary to complete the internal register programming.
october 2005 version 1.2 fme/ms/dac80/ds/4972 mb86064 dual 14-bit 1gsa/s dac page 18 of 52 production copyright ? 2004-2005 fujitsu microelectronics europe gmbh disclaimer : the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales repr esentatives before ordering.the information and circuit diagrams in this document are presented ?as is?, no license is grant ed by implication or otherwise. figure 10 serial control interface ?write? operation figure 11 serial control interface ?read? operation serial_clk serial_in serial_en serial_out address new data in old data out reg bit n - - - - - - - - - - - - - - - reg bit 0 zero-fill msb lsb msb lsb msb lsb w example of zero-filling a register serial_clk serial_in serial_en serial_out address data out reg bit n - - - - - - - - - - - - - - - reg bit 0 zero-fill msb lsb msb lsb r
october 2005 version 1.2 fme/ms/dac80/ds/4972 mb86064 dual 14-bit 1gsa/s dac copyright ? 2004-2005 fujitsu microelectronics europe gmbh production page 19 of 52 disclaimer : the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales repr esentatives before ordering.the information and circuit diagrams in this document are presented ?as is?, no license is grant ed by implication or otherwise. figure 12 serial control interface timing requirements for initial testing & evaluation it is assumed that customers will use the fujitsu pc usb programming cable and software, both with the product development kit and for initial target application debug. see section 7 for further information. serial_clk serial_in t sihld t sisu serial_out t sov v ih & serial_en
october 2005 version 1.2 fme/ms/dac80/ds/4972 mb86064 dual 14-bit 1gsa/s dac page 20 of 52 production copyright ? 2004-2005 fujitsu microelectronics europe gmbh disclaimer : the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales repr esentatives before ordering.the information and circuit diagrams in this document are presented ?as is?, no license is grant ed by implication or otherwise. 3 waveform memory module enabling the waveform memory module allows interleaving of the lvds data to drive a single dac core as well as access to any downloaded waveforms. the on-chip waveform memories allow the dac cores to be exercised with user programmable waveforms without the need for an external high speed pattern generator. the memories are physically implemented using four 2k x 64-bit static rams, assigned as two per dac for odd and even samples. the memories can be configured to drive two different waveforms of equal length, up to 16k points each, to be routed to dac a and dac b independently. alternatively, it is possible to download multiple waveforms, totalling 16k points or less, to be selected as required. this last configuration takes advantage of the ability to specify the waveform start address and length. data routing within the waveform memory module is determined by three cascaded multiplexers, mux_[a/b/c]_ctrl[0:2], as illustrated in figure 13. figure 13 waveform memory module data routing waveform memory a 16k x 16-bit (even & odd) waveform memory a 16k x 16-bit (even & odd) waveform memory b 16k x 16-bit (even & odd) waveform memory b 16k x 16-bit (even & odd) waveform memory module data_direct 0x00 - pg12 mux_a_ctrl[2] mux_b_ctrl[2] port a data input 14-bit lvds port b data input 14-bit lvds en_int_term 0x1c4 - pg11 en_int_term 0x1c4 - pg11 mux 0 mux 0 mux 1 mux 1 mux2 mux2 mux_a_ctrl[1] mux_a_ctrl[0] mux_b_ctrl[0] mux_b_ctrl[1] even even odd odd dac b (14-bit) dac a (14-bit)
october 2005 version 1.2 fme/ms/dac80/ds/4972 mb86064 dual 14-bit 1gsa/s dac copyright ? 2004-2005 fujitsu microelectronics europe gmbh production page 21 of 52 disclaimer : the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales repr esentatives before ordering.the information and circuit diagrams in this document are presented ?as is?, no license is grant ed by implication or otherwise. the data multiplexers are controlled by the wmm registers, wmm [even/odd] mux ctrl. setting of these registers is referred to in the following two sections. to use any of the waveform memory module modes it is necessary to first enable the module?s clock through register system misc, bit en_wmm_clk (see table 13). table 12: waveform memory module register: wmm [even/odd] mux ctrl [0x11/0x21] wmm [even/ odd] mux ctrl (bit) label function 0 mux_a_ctrl[0] mux 0 control bit 0 = data from lvds input port a (default) 1 = data from mux 1 1 mux_a_ctrl[1] mux 1 control bit 0 = data from lvds input port b (default) 1 = data from mux 2 2 mux_a_ctrl[2] mux 2 control bit (1). see also mux_a_ctrl[3] setting. 0 = data from ram a - 16k points mode (default) 1 = not used 3 mux_a_ctrl[3] mux 2 control bit (2) 0 = mux_a_ctrl[2] operates as normal (default) 1 = when mux_a_ctrl[2] = 0, ram b is used instead of ram a 4 mux_b_ctrl[0] mux 0 control bit 0 = data from lvds input port b (default) 1 = data from mux 1 5 mux_b_ctrl[1] mux 1 control bit 0 = data from lvds input port a (default) 1 = data from mux 2 6 mux_b_ctrl[2] mux 2 control bit (1). see also mux_b_ctrl[3] setting. 0 = data from ram b - 16k points mode (default) 1 = not used 7 mux_b_ctrl[3] mux 2 control bit (2) 0 = mux_b_ctrl[2] operates as normal (default) 1 = when mux_b_ctrl[2] = 0, ram a is used instead of ram b table 13: dac core register: system misc [0x1c4] (part 3 of 3) system misc (bit) label function 1 en_wmm_clk waveform memory module clock control 0 = enabled, 1 = disabled (default)
october 2005 version 1.2 fme/ms/dac80/ds/4972 mb86064 dual 14-bit 1gsa/s dac page 22 of 52 production copyright ? 2004-2005 fujitsu microelectronics europe gmbh disclaimer : the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales repr esentatives before ordering.the information and circuit diagrams in this document are presented ?as is?, no license is grant ed by implication or otherwise. 3.1 dual port, interleaved lvds data via the wmm by routing the external lvds data through the waveform memory module it is possible to interleave a and b data into one of the dac cores. to configure the device in this mode even & odd multiplexers need to be set differently. table 14: configuration for interleaved data to dac a table 15: configuration for interleaved data to dac b remember to set register wmm config [0x00] bit data_direct to ?1? (see table 9) the dac will now sample both input ports, for consecutive dac samples, as the even and odd routing through the waveform memory module is not the same. figure 14 interleaved mode odd and even data sampling wmm even mux ctrl [0x11] wmm odd mux ctrl [0x21] dac a mux_a_ctrl[0] (bit 0) mux_a_ctrl[0] (bit 0) odd data in even data in ?1? ?0? (default) port a port b ?0? (default) ?1? port b port a wmm even mux ctrl [0x11] wmm odd mux ctrl [0x21] dac b mux_b_ctrl[0] (bit 4) mux_a_ctrl[0] (bit 4) odd data in even data in ?1? ?0? (default) port b port a ?0? (default) ?1? port a port b odd data even data d n+1 d n=0 d n+3 d n+2 d n+5 d n+4 clock output
october 2005 version 1.2 fme/ms/dac80/ds/4972 mb86064 dual 14-bit 1gsa/s dac copyright ? 2004-2005 fujitsu microelectronics europe gmbh production page 23 of 52 disclaimer : the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales repr esentatives before ordering.the information and circuit diagrams in this document are presented ?as is?, no license is grant ed by implication or otherwise. 3.2 waveform memory module operation to make full use of the waveform memory module user waveforms may be downloaded to the on- chip memories. different waveforms of equal length may be stored in each ram, totalling up to 16k points (in multiples of eight points). configuration of the wmm [even/odd] mux ctrl registers will determine which vector is routed to which dac. before the waveform memories can be used they must be enabled through register wmm [even/odd] config, bit ram_ih . see table 16. figure 15 waveform memories routing diagram table 16: wmm register: wmm [even/odd] config [0x10/0x20] (part 1 of 2) wmm [even/ odd] config (bit) label function 1 ram_ih waveform memory inhibit control 0 = memories enabled 1 = memories disabled (default) waveform memory module mux_a_ctrl[3] mux_b_ctrl[3] mux 1 even mux 2 even mux 2 odd mux 2 even ram a even ram b even ram a odd ram b odd mux 2 odd mux 1 odd mux 1 even mux 1 odd ram access controller ram access controller ram access controller ram access controller to dac b, via mux 0 to dac a, via mux 0 mux_b_ctrl[2] mux_b_ctrl[2] mux_a_ctrl[2] mux_a_ctrl[2]
october 2005 version 1.2 fme/ms/dac80/ds/4972 mb86064 dual 14-bit 1gsa/s dac page 24 of 52 production copyright ? 2004-2005 fujitsu microelectronics europe gmbh disclaimer : the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales repr esentatives before ordering.the information and circuit diagrams in this document are presented ?as is?, no license is grant ed by implication or otherwise. odd and even ram elements within the module allow data to be routed to the odd and even phase dac core data latches, similar to when data is input via the lvds data interface and double edge clocking is used. as an example, to route data from ram a to dac a, and ram b to dac b, set register wmm [even/odd] mux ctrl bits mux_a_ctrl[1] & [0] and mux_b_ctrl[1] & [0] . both the even and odd registers should be set the same. all other bits should be set to their default value. to swap these data paths, set register wmm [even/odd] mux ctrl bits mux_a_ctrl[3] and mux_b_ctrl[3]. both the even and odd registers should be set the same. 3.2.1 waveform memory access via the serial interface to access the waveform memories the ram access controllers must first be configured. the ram access controllers are configured through registers wmm [even/odd] ram ctrl. see table 17. when programming the wmm on-chip memories ensure that the clock input (f clk ) is greater than 16 times the serial interface clock frequency (f sclk ) for correct operation. table 17: waveform memory module registers: wmm [even/odd] ram ctrl [0x12/0x22] wmm [even/ odd] ram ctrl (bits) label function [10:0] prog_addr ram access start address [21:11] prog_burst ram access burst size access burst size should be programmed as ((no. of points/8) - 1) a value of zero indicates a single word access 22 prog_rw ram serial interface access mode 0 = read mode (default) 1 = write mode 23 prog_sel(1) ram write select (1). dependent on prog_sel(2) setting 0 = write data to ram a (default) 1 = write data to ram b 24 prog_sel(2) ram write select (2) 0 = prog_sel(1) operates as normal (default) 1 = writes the same data to both ram a and ram b 25 prog_start ram access controller control 0 = cycle through vector address range (default) 1 = program rams this bit is self clearing
october 2005 version 1.2 fme/ms/dac80/ds/4972 mb86064 dual 14-bit 1gsa/s dac copyright ? 2004-2005 fujitsu microelectronics europe gmbh production page 25 of 52 disclaimer : the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales repr esentatives before ordering.the information and circuit diagrams in this document are presented ?as is?, no license is grant ed by implication or otherwise. the wmm [even/odd] ram ctrl registers prog_addr fields are used to define the start address of the waveform. these fields should be set to 0 in order to store a full 16k point waveform. for the multiple waveform mode, the number entered into these fields is the start location within the 2k x 64- bit odd/even ram element that the waveform is to be stored. one address location in this field translates to eight waveform vector points because four points are stored at each address of the odd and even ram blocks. the wmm [even/odd] ram ctrl registers prog_burst fields sets the length of the stored waveform, defined as the number of waveform points divided by eight, minus one. every ram address in each of the odd, even, ram a and ram b memories corresponds to a 64-bit location. each location is divided into four 16-bit samples. figure 16 shows an example of how a 32 point vector is stored. in this example prog_addr is set to 0 and prog_burst = 3. figure 16 waveform vector storage in on-chip memories prog_addr and prog_burst must be the same for ram a and ram b when routing data to the dacs. register bit prog_rw is used to select between reading from and writing to the rams through the serial interface. this bit should be set to ?1? to write data into the rams, but does not need to be cleared to route data out to the dacs. bit prog_rw only needs to be cleared if data in the rams is to be read out through the serial interface. register bit prog_sel(1) selects between ram a and ram b when data is being written or read via the serial interface. this bit has no function when data is being read out to the dacs. register bit prog_sel(2) allows the data to be written to both ram a and ram b simultaneously. 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 0 1 2 3 4 5 6 7 ram a even ram a odd 8 9 10 11 28 29 30 31 0 1 2 3 4 address location prog_burst = 3 waveform samples.... prog_addr = 0 0 63 0 63
october 2005 version 1.2 fme/ms/dac80/ds/4972 mb86064 dual 14-bit 1gsa/s dac page 26 of 52 production copyright ? 2004-2005 fujitsu microelectronics europe gmbh disclaimer : the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales repr esentatives before ordering.the information and circuit diagrams in this document are presented ?as is?, no license is grant ed by implication or otherwise. register bit prog_start is used to indicate the start of a write cycle to the rams. this bit is self clearing. see section 3.2.2 for details of the write cycle. 3.2.2 writing data into the memories the process of writing data into the rams is controlled by the ram access controllers, which expect data to be presented through the serial interface in a set sequence through the wmm [even/odd] ram data registers. the ram access controllers will expect to receive the number of ram data words specified in the register wmm [even/odd] ram ctrl prog_burst field. if additional ram data words are sent, the data will be ignored. however, if less than the specified number of data words is sent, the ram access controller will not return to the idle state until the sequence has been completed by receipt of the correct number of ram data words. this will corrupt the sequence in the ram if the next ram data word received is not intended for that ram element. a write sequence may be terminated early with a software reset (see section 3.3). the 64-bit wide wmm [even/odd] ram data registers are used to transfer pre-formatted data into the ram address location selected by the ram access controller. see table 18. the 14-bit dac data should be msb aligned to the 15th bit of the waveform sample (dac data d14 aligned to waveform bit 14 [15:0], i.e. register bits 0, 15, 16, 31, 32, 47, 48, 63 etc. are not used). the following sequence could be followed, write the first pre-formatted ram data word to register wmm even ram data write to register wmm even ram ctrl with bit prog_start set consecutively write the remaining ram data words to register wmm even ram data. table 18: waveform memory module registers: wmm [even/odd] ram data [0x13/0x23] wmm even ram data (bits) label function [15:0] prog_data waveform even sample word n [31:16] waveform even sample word n+2 [47:32] waveform even sample word n+4 [63:48] waveform even sample word n+6 wmm odd ram data (bits) label function [15:0] prog_data waveform odd sample word n+1 [31:16] waveform odd sample word n+3 [47:32] waveform odd sample word n+5 [63:48] waveform odd sample word n+7
october 2005 version 1.2 fme/ms/dac80/ds/4972 mb86064 dual 14-bit 1gsa/s dac copyright ? 2004-2005 fujitsu microelectronics europe gmbh production page 27 of 52 disclaimer : the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales repr esentatives before ordering.the information and circuit diagrams in this document are presented ?as is?, no license is grant ed by implication or otherwise. once the ram access controller returns to the idle state, after a successful write sequence, data transfer starts automatically. however, until the other ram element is programmed and the rams are synchronised, the output sequence will be corrupt. repeat the above sequence for the odd ram element. the order in which the even/odd rams are programmed is not important. once all of the required rams have been programmed, the ram access controllers need to be set to ?run? and synchronised by a software reset, see section 3.3. finally, ensure that all odd, even and the wmm/lvds data multiplexers are set appropriately. a worked example is given in section 6.5.4 programming the wmm / lvds data source multiplexer bit ? data_direct ? last will prevent incomplete and unsynchronised data reaching the dac before it is required. 3.3 software reset the waveform memory module may be reset through a software reset function. this is activated through register bist [even/odd] config bit swrst . two writes to ? swrst ? are required to produce a software reset; first setting (1) and then clearing (0). writing to both odd and even registers (0x10 or 0x20) is not necessary as either register will synchronise all memories. table 19: wmm register: wmm [even/odd] config [0x10/0x20] (part 2 of 2) wmm [even/ odd] config (bit) label function 0swrst software reset control bit 0 = normal operation (default) , 1 = software reset
october 2005 version 1.2 fme/ms/dac80/ds/4972 mb86064 dual 14-bit 1gsa/s dac page 28 of 52 production copyright ? 2004-2005 fujitsu microelectronics europe gmbh disclaimer : the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales repr esentatives before ordering.the information and circuit diagrams in this document are presented ?as is?, no license is grant ed by implication or otherwise. 4 electrical characteristics 4.1 absolute maximum ratings 4.2 digital interface specifications parameter notes symbol ratings units min. typ. max. supply voltage analog supply v avd33 3.6 v digital supply v dvdd 2.0 v input voltage lvds inputs v lvds v dvss -0.5 v dvdd +0.5 v digital control inputs v con v dvss -0.5 v dvdd +0.5 v analog output voltage v o v dvss -1 v dvdd +0.5 v analog output current 1 o +25 ma storage temperature t st -40 +85 o c junction temperature t j -40 +125 o c t a (min) to t a (max), avd33 = +3.3v, avss = 0v, dvdd = +1.8v, dvss = 0v, i fs = 20ma. 1. iout & ioutb avss - 0.5v to avd18 + 0.5v parameter notes symbol ratings units min. typ. max. cmos control inputs high-level input voltage v ih 1.2 v dvdd v low-level input voltage v il v dvss 0.6 v cmos control outputs high-level output voltage 1 v oh v dvdd - 0.275 v low-level output voltage 2 v ol v dvss + 0.225 v lvds data inputs common mode input voltage v cm 0.9 1.4 v differential input voltage v id 100 350 600 mv setup time 3 t s -0.4 -0.6 ns hold time 3 t h 0.9 1.4 ns t a (min) to t a (max), avd33 = +3.3v, avss = 0v, dvdd = +1.8v, dvss = 0v 1. i oh = +4ma 2. i ol = -4ma 3. referenced to the input clock (clkin) & with dac_clk_dly = 0x00
october 2005 version 1.2 fme/ms/dac80/ds/4972 mb86064 dual 14-bit 1gsa/s dac copyright ? 2004-2005 fujitsu microelectronics europe gmbh production page 29 of 52 disclaimer : the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales repr esentatives before ordering.the information and circuit diagrams in this document are presented ?as is?, no license is grant ed by implication or otherwise. 4.3 dc specifications parameter notes symbol ratings units min. typ. max. dc accuracy integral non linearity inl 1.1 2.0 lsb 14 differential non linearity dnl 0.6 1.0 lsb 14 analog output full scale signal output current op +20 ma current at each output 5 15 25 ma load resistance (single ended) r l 16.5 50 ? output resistance 330 k ? output capacitance 22 pf gain error 0.15 %fs output voltage (compliance) - maximum -1.0 +0.5 v output voltage (compliance) - best performance -0.8 +0.2 v output power supply rejection ratio psrr due to variation in analog supply (external vref) 1 0.01 % due to variation in analog supply (internal vref) 1 0.02 % internal bandgap reference reference voltage v bg 1.15 1.2 1.25 v reference output current i bg 0 100 a reference output voltage variation 1 0.01 % external reference input reference voltage v ref 1.10 1.30 v reference input current i bg -1 +1 a thermal ambient temperature t a -40 25 +85 o c storage temperature t s 5+30 o c package thermal resistance junction to pcb (top side) j-pcb 4 o c/w junction to ambient (estimate - pcb dependant) 2 ja 20 o c/w t a (min) to t a (max), avd33 = +3.3v, avss = 0v, dvdd = +1.8v, dvss = 0v, i fs = 20ma. 1. v avd33 (min) to v avd33 (max) 2. refer to section 6.1
october 2005 version 1.2 fme/ms/dac80/ds/4972 mb86064 dual 14-bit 1gsa/s dac page 30 of 52 production copyright ? 2004-2005 fujitsu microelectronics europe gmbh disclaimer : the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales repr esentatives before ordering.the information and circuit diagrams in this document are presented ?as is?, no license is grant ed by implication or otherwise. 4.4 ac specifications parameter notes symbol ratings units min. typ. max. spurious-free dynamic range sfdr single tone at -1dbfs, 800msa/s, dc to 400mhz 1 20 mhz 75 dbc 40 mhz 72 dbc 70 mhz 66 dbc 140 mhz 62 dbc 300 mhz 58 dbc single tone at -1dbfs, 1gsa/s, dc to 500mhz 1 20 mhz 84 dbc 40 mhz 80 dbc 70 mhz 76 dbc 140 mhz 68 dbc 300 mhz 61 dbc single tone at -1dbfs, 800msa/s, dc to 400mhz 2 20 mhz 84 dbc 40 mhz 79 dbc 70 mhz 75 dbc 140 mhz 70 76 dbc 300 mhz 72 dbc single tone at -1dbfs, 1gsa/s, dc to 500mhz 2 20 mhz 84 dbc 40 mhz 81 dbc 70 mhz 77 dbc 140 mhz 73 dbc 300 mhz 74 dbc single tone at -1dbfs, 800msa/s, 100mhz 300 mhz 79 dbc inter-modulation distortion 3imd 4 tones, ea. -12dbfs, missing centre tone at 70mhz 89 dbc 140mhz 75 85 dbc 255mhz 75 dbc
october 2005 version 1.2 fme/ms/dac80/ds/4972 mb86064 dual 14-bit 1gsa/s dac copyright ? 2004-2005 fujitsu microelectronics europe gmbh production page 31 of 52 disclaimer : the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales repr esentatives before ordering.the information and circuit diagrams in this document are presented ?as is?, no license is grant ed by implication or otherwise. 4.5 dynamic performance adjacent channel leakage ratio aclr 1 x umts carrier, 5mhz channel spacing 30.72mhz centre frequency, 245.76msa/s 84 dbc 276.48mhz centre frequency, 737.28msa/s 76 dbc 4 x umts carriers, 5mhz channel spacing 276.48mhz centre frequency, 737.28msa/s 69 74 dbc images interleaved dac image f clk - f sig 40 30 dbc 2nd order interleaved dac image f clk - 2.f sig 57 50 dbc t a (min) to t a (max), avd33 = +3.3v, avss = 0v, dvdd = +1.8v, dvss = 0v, i fs = 20ma, differential transformer coupled output presenting 33 ? effective differential load, filtered sinewave clock unless otherwise specified. 1. excludes f clk & f clk -f out image 2. excludes f clk , f clk -f out & f clk -2.f out images 3. 240khz tone spacing with non-aligned phase alignment. peak to rms = 6.4db. 800msa/s parameter notes symbol ratings units min. typ. max. analog output clk in to analog out delay (to 0.1%) t o 4.1 ns output settling time (to 0.1%) t set 1.8 ns output rise time (10% to 90%) t r 0.6 ns output fall time (90% to 10%) t f 0.6 ns noise floor single tone at -1dbfs, 624msa/s 20 mhz tone -166 dbm/hz 247 mhz tone -159 dbm/hz 300 mhz tone 1 -156 dbm/hz clock feed-through f clkop -46 -42 dbm crosstalk 26467dbc t a (min) to t a (max), avd33 = +3.3v, avss = 0v, dvdd = +1.8v, dvss = 0v, i fs = 20ma, differential transformer coupled output presenting 33 ? effective differential load, filtered sinewave clock unless otherwise specified. 1. in snr terms compares to -159dbm/hz for 500msa/s dac or -163dbm/hz for 400msa/s. 2. measured using 4 tone test, each tone at -15dbfs with 1.2mhz spacing, centred at 276mhz 4mhz parameter (continued) notes symbol ratings units min. typ. max.
october 2005 version 1.2 fme/ms/dac80/ds/4972 mb86064 dual 14-bit 1gsa/s dac page 32 of 52 production copyright ? 2004-2005 fujitsu microelectronics europe gmbh disclaimer : the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales repr esentatives before ordering.the information and circuit diagrams in this document are presented ?as is?, no license is grant ed by implication or otherwise. 4.6 clock specifications parameter notes symbol ratings units min. typ. max. clock input maximum clock frequency f clk 500 600 mhz square wave low time t lo 0.95 1 ns high time t hi 0.95 1 ns slew rate for minimum wide-band jitter t sl 0.5 v/ns clock input duty cycle 1 50 % low-level input voltage v il v dvss - 200mv v high-level input voltage v ih v dvdd + 200mv v sinusoidal (recommended) common mode input voltage v cm 0.9 1.2 1.8 v signal level (f clk = 312mhz) 2 -2 4 +10 dbm clock outputs (lvds) common mode output voltage 3 v cm 0.5 1.1 1.2 v differential output voltage 3 & 4 v od 320 350 550 mv delay, clkin to clkx_out 5 t clko 2.9 ns jitter added, clkin to clkx_out (rms) 6 5 ps jitter added, clkin to clkx_out (pk-pk) 6 30 ps loop clock (lvds) delay, lpclk_in to lpclk_out 7 t lplclk 1.3 ns t a (min) to t a (max), avd33 = +3.3v, avss = 0v, dvdd = +1.8v, dvss = 0v 1. ensure clock input symmetry to obtain best performance. deviation from this will increase fclk related images. 2. power into 100r termination. 3. also applies to loop clock output. 4. r t = 50 ? ( double 100 ? termination) across the lvds q and q signals. 5. assumes ?clkoutx_clk_dly? is set to its minimum (default) setting. 6. at 500mhz. assumes ?clkoutx_clk_dly? is set to its minimum (default) setting. 7. assumes ?loop_clk_dly? is set to its minimum (default) setting. caution electrostatic discharge sensitive device high electrostatic charges can accumulate in the human body and discharge without detection. ensure proper esd procedures are followed when handling this device.
october 2005 version 1.2 fme/ms/dac80/ds/4972 mb86064 dual 14-bit 1gsa/s dac copyright ? 2004-2005 fujitsu microelectronics europe gmbh production page 33 of 52 disclaimer : the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales repr esentatives before ordering.the information and circuit diagrams in this document are presented ?as is?, no license is grant ed by implication or otherwise. 4.7 serial interface timing specifications 4.8 power consumption parameter notes symbol ratings units min. typ. max. serial clock frequency 1f sclk 010mhz serial clock mark or space 20 ns setup , serial_in to serial_clk rising edge t sisu 3ns hold , serial_in from serial_clk rising edge t sihld 3ns delay , serial_clk to serial_out valid t sov 422ns t a (min) to t a (max), avd33 = +3.3v, avss = 0v, dvdd = +1.8v, dvss = 0v 1. when programming the wmm on-chip memories f clk > 16 x f sclk for correct operation. parameter notes symbol ratings units min. typ. max. power supply 1 analog supply (avd33) v avd33 3.1 3.3 3.5 v single dac, 500mhz / 1gsa/s, lvds data 2 i avd33 83 106 ma dual dac, 500mhz / 1gsa/s, lvds data 2 140 179 ma digital supply (dvdd) v dvdd 1.7 1.8 1.9 v single dac, 500mhz / 1gsa/s, lvds data 2 i dvdd 265 338 ma dual dac, 500mhz / 1gsa/s, lvds data 2, 3 460 587 ma power dissipation 1, 4 p d single dac, 400mhz / 800msa/s, lvds data 650 755 mw dual dac, 400mhz / 800msa/s, lvds data 1,120 1,300 mw single dac, 500mhz / 1gsa/s, lvds data 750 870 mw dual dac, 400mhz / 800msa/s, wmm mode 1,660 1,865 mw t a (min) to t a (max), avd33 = +3.3v, avss = 0v, dvdd = +1.8v, dvss = 0v, i fs = 20ma. 1. current consumption and power dissipation are data related. maximum figures are by evaluation. 2. see figure 17. 3. with wmm enabled power consumption is ~ +76ma / 100mhz (typ.) +86ma / 100mhz (max.) 4. see figure 18.
october 2005 version 1.2 fme/ms/dac80/ds/4972 mb86064 dual 14-bit 1gsa/s dac page 34 of 52 production copyright ? 2004-2005 fujitsu microelectronics europe gmbh disclaimer : the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales repr esentatives before ordering.the information and circuit diagrams in this document are presented ?as is?, no license is grant ed by implication or otherwise. figure 17 current consumption figure 18 power consumption 0 100 200 300 400 500 600 300 350 400 450 500 550 600 clock frequency (mhz) current consumption (ma) max. dvdd (dual) typ. dvdd (dual) max. dvdd (single) typ. dvdd (single) max. avdd (dual) typ. avdd (dual) max. avdd (single) typ. avdd (single) 400 600 800 1,000 1,200 1,400 1,600 1,800 300 350 400 450 500 550 600 clock frequency (mhz) power consumption (mw) max. pd (dual) typ. pd (dual) max. pd (single) typ. pd (single)
october 2005 version 1.2 fme/ms/dac80/ds/4972 mb86064 dual 14-bit 1gsa/s dac copyright ? 2004-2005 fujitsu microelectronics europe gmbh production page 35 of 52 disclaimer : the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales repr esentatives before ordering.the information and circuit diagrams in this document are presented ?as is?, no license is grant ed by implication or otherwise. 5 mechanical data 5.1 pin assignment e3 e1 f4 f2 g3 g1 h4 h2 j3 j1 k4 k2 l3 l1 m4 m2 n3 n1 p4 p2 r3 r1 t4 t2 u3 v2 w3 w1 aa5 ac5 y6 ab6 aa7 ac7 y8 ab8 aa9 ac9 y10 ab10 aa11 ac11 y12 ab12 aa13 ac13 y14 ab14 aa15 ac15 y16 ab16 aa17 ac17 y18 ab18 aa19 ac19 w21 w23 v20 v22 u21 u23 t20 t22 r21 r23 p20 p22 n21 n23 m20 m22 l21 l23 k20 k22 j21 j23 h20 h22 g21 g23 f20 f22 e21 e23 c19 a19 d18 b18 c17 a17 b16 d16 a15 c15 b14 d14 a13 c13 b12 d12 a11 c11 b10 d10 a9 c9 b8 a7 c7 d8 b6 d6 a5 c5 index n10 n12 n14 r10 r12 r14 l10 l12 l14 j10 j12 j14 k9 k11 k13 k15 m9 m11 m13 m15 p9 p11 p13 p15 serial_in serial_en avss ioutb_b iout_b avd33 bgap avd18_clk avd25 avd33 iout_a ioutb_a avss dac_scan spare clkin clkinb vlow_a avd18_a avd18_a x_reset test vlow_b x_a10 vref rref avss serial_out serial_clk avd18_b avd18_b a10 dvss dvdd dvdd dvss a8 a6 x_a8 x_a6 a2 x_a2 a4 dvdd x_b9 dvss x_a4 b9 x_b10 b10 dvdd dvss dvdd dvss dvdd dvss x_a3 a3 a1 nc x_a1 dvss nc a5 x_a5 a7 x_a7 dvdd a9 x_a9 b13 x_b13 dvss lpclk_out a13 x_lpclk_in lpclk_in x_lpclk_out x_a13 dvss x_a11 a11 clk1_out a14 dvdd x_a12 x_clk1_out x_a14 a12 b11 dvss x_b14 clk2_out dvdd x_b12 dvdd b14 b12 x_b11 b6 x_b6 b8 x_b8 b2 x_b2 x_b3 b1 b3 dvdd x_b4 b5 nc x_b1 dvss b4 x_b5 b7 x_b7 nc u1 v4 not to scale. viewed from above. all centre pins : tg x_clk2_out
october 2005 version 1.2 fme/ms/dac80/ds/4972 mb86064 dual 14-bit 1gsa/s dac page 36 of 52 production copyright ? 2004-2005 fujitsu microelectronics europe gmbh disclaimer : the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales repr esentatives before ordering.the information and circuit diagrams in this document are presented ?as is?, no license is grant ed by implication or otherwise. 5.2 pin definition analog and clock interface thermal / ground array pin nos. pin name input/ output description note d10, d14 avd33 power analog positive supply, +3.3v decouple to avss b16, a17 avd18_a o dac ?a? internal 1.8v regulator output decouple to avss a7, b8 avd18_b o dac ?b? internal 1.8v regulator output decouple to avss d12 avd18_clk o input clock internal 1.8v regulator output decouple to avss c7, b12, c17 avss power analog ground, 0v c15 iout_a o positive analog output, dac ?a? d16 ioutb_a o negative analog output, dac ?a? c9 iout_b o positive analog output, dac ?b? d8 ioutb_b o negative analog output, dac ?b? c11 bgap o bandgap reference output refer to section 1.4 b10 vref i voltage reference input refer to section 1.4 a11 rref o analog output current reference resistor refer to section 1.5 c13 avd25 o regulated 2.5v output (supply for external voltage reference) decouple to avss a15 vlo_a o dac ?a? clock reference level decouple to avd18_a a9 vlo_b o dac ?b? clock reference level decouple to avd18_b a13 clkin i clock input, positive input requires biasing - refer to section 6.2 b14 clkinb i clock input, negative input ac13 clk1_out o lvds output clock #1, positive output use double termination ab14 x_clk1_out o lvds output clock #1, negative output ac11 clk2_out o lvds output clock #2, positive output use double termination ab10 x_clk2_out o lvds output clock #2, negative output aa11 lpclk_in i lvds calibration loop clock, positive input y10 x_lpclk_in i lvds calibration loop clock, negative input aa13 lpclk_out o lvds calibration loop clock, positive output use double termination y14 x_lpclk_out o lvds calibration loop clock, negative output pin nos. pin name input/ output description note j10, j12, j14, k9, k11, k13, k15, l10, l12, l14, m9, m11, m13, m15, n10, n12, n14, p9, p11, p13, p15, r10, r12, r14 tg - thermal / ground array connection connect to the dvss digital ground plane
october 2005 version 1.2 fme/ms/dac80/ds/4972 mb86064 dual 14-bit 1gsa/s dac copyright ? 2004-2005 fujitsu microelectronics europe gmbh production page 37 of 52 disclaimer : the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales repr esentatives before ordering.the information and circuit diagrams in this document are presented ?as is?, no license is grant ed by implication or otherwise. digital data interface pin nos. pin name input/ output description note f2, f22, g1, m2, u1, ac7, ab12, ac17, u23, m22, g23 dvdd power digital positive supply, +1.8v decouple to dvss. n.b. f2 & f22 are not power supplies but should be connected to dvdd. e1, e23, g3, m4, u3, aa7, y12, aa17, u21, m20, g21 dvss power digital ground, 0v n.b. e1 & e23 are not power supplies but should be connected to dvss. h20 a1 i dac ?a? bit 1 lvds positive input lsb j21 x_a1 i dac ?a? bit 1 lvds negative input h22 a2 i dac ?a? bit 2 lvds positive input j23 x_a2 i dac ?a? bit 2 lvds negative input k20 a3 i dac ?a? bit 3 lvds positive input l21 x_a3 i dac ?a? bit 3 lvds negative input k22 a4 i dac ?a? bit 4 lvds positive input l23 x_a4 i dac ?a? bit 4 lvds negative input n23 a5 i dac ?a? bit 5 lvds positive input p22 x_a5 i dac ?a? bit 5 lvds negative input n21 a6 i dac ?a? bit 6 lvds positive input p20 x_a6 i dac ?a? bit 6 lvds negative input r23 a7 i dac ?a? bit 7 lvds positive input t22 x_a7 i dac ?a? bit 7 lvds negative input r21 a8 i dac ?a? bit 8 lvds positive input t20 x_a8 i dac ?a? bit 8 lvds negative input v22 a9 i dac ?a? bit 9 lvds positive input w23 x_a9 i dac ?a? bit 9lvds negative input v20 a10 i dac ?a? bit 10 lvds positive input w21 x_a10 i dac ?a? bit 10 lvds negative input aa19 a11 i dac ?a? bit 11 lvds positive input y18 x_a11 i dac ?a? bit 11 lvds negative input ac19 a12 i dac ?a? bit 12 lvds positive input ab18 x_a12 i dac ?a? bit 12 lvds negative input y16 a13 i dac ?a? bit 13 lvds positive input aa15 x_a13 i dac ?a? bit 13 lvds negative input ab16 a14 i dac ?a? bit 14 lvds positive input msb ac15 x_a14 i dac ?a? bit 14 lvds negative input h4 b1 i dac ?b? bit 1 lvds positive input lsb j3 x_b1 i dac ?b? bit 1 lvds negative input h2 b2 i dac ?b? bit 2 lvds positive input j1 x_b2 i dac ?b? bit 2 lvds negative input k4 b3 i dac ?b? bit 3 lvds positive input l3 x_b3 i dac ?b? bit 3 lvds negative input k2 b4 i dac ?b? bit 4 lvds positive input
october 2005 version 1.2 fme/ms/dac80/ds/4972 mb86064 dual 14-bit 1gsa/s dac page 38 of 52 production copyright ? 2004-2005 fujitsu microelectronics europe gmbh disclaimer : the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales repr esentatives before ordering.the information and circuit diagrams in this document are presented ?as is?, no license is grant ed by implication or otherwise. digital control interface l1 x_b4 i dac ?b? bit 4 lvds negative input n1 b5 i dac ?b? bit 5 lvds positive input p2 x_b5 i dac ?b? bit 5 lvds negative input n3 b6 i dac ?b? bit 6 lvds positive input p4 x_b6 i dac ?b? bit 6 lvds negative input r1 b7 i dac ?b? bit 7 lvds positive input t2 x_b7 i dac ?b? bit 7 lvds negative input r3 b8 i dac ?b? bit 8 lvds positive input t4 x_b8 i dac ?b? bit 8 lvds negative input v2 b9 i dac ?b? bit 9 lvds positive input w1 x_b9 i dac ?b? bit 9 lvds negative input v4 b10 i dac ?b? bit 10 lvds positive input w3 x_b10 i dac ?b? bit 10 lvds negative input aa5 b11 i dac ?b? bit 11 lvds positive input y6 x_b11 i dac ?b? bit 11 lvds negative input ac5 b12 i dac ?b? bit 12 lvds positive input ab6 x_b12 i dac ?b? bit 12 lvds negative input y8 b13 i dac ?b? bit 13 lvds positive input aa9 x_b13 i dac ?b? bit 13 lvds negative input ab8 b14 i dac ?b? bit 14 lvds positive input msb ac9 x_b14 i dac ?b? bit 14 lvds negative input pin nos. pin name input/ output description note b18 x_reset i device reset ?0? = reset c5 serial_in i serial interface serial data input a5 serial_out o serial interface serial data output b6 serial_clk i serial interface serial data clock d6 serial_en i serial interface enable d18 dac_scan i fujitsu test pin connect to dvss c19 spare i fujitsu test pin connect to dvss a19 test i fujitsu test pin connect to dvss e21 nc - no connect e3 nc - no connect f4 nc - no connect f20 nc - no connect pin nos. pin name input/ output description note
october 2005 version 1.2 fme/ms/dac80/ds/4972 mb86064 dual 14-bit 1gsa/s dac copyright ? 2004-2005 fujitsu microelectronics europe gmbh production page 39 of 52 disclaimer : the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales repr esentatives before ordering.the information and circuit diagrams in this document are presented ?as is?, no license is grant ed by implication or otherwise. 5.3 package data dimensions in millimetres. ball array viewed from below . important: this device requires pre-baking at 125c (257f) for 24 hours before mounting unless removed from approved vacuum sealed packaging just prior to assembly. 5.4 ordering information the following reference should be used when ordering devices, mb86064pb-g MB86064PB-GE1 lead-free package variant shipment is in plastic trays, each capable of holding 168 devices. for further assistance please contact your fujitsu microelectronics? sales representative.
october 2005 version 1.2 fme/ms/dac80/ds/4972 mb86064 dual 14-bit 1gsa/s dac page 40 of 52 production copyright ? 2004-2005 fujitsu microelectronics europe gmbh disclaimer : the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales repr esentatives before ordering.the information and circuit diagrams in this document are presented ?as is?, no license is grant ed by implication or otherwise. 6 application notes 6.1 pcb power & ground plane splits and decoupling the following guidelines are suggestions to help obtain best performance from the mb86064. the information may be subject to change. the ground plane should not be split into the digital and analog regions. the digital and analog power planes must be split as these are different voltages. even though a common ground plane is recommended, ?analog? and ?digital? grounds should not be linked on the top surface of the pcb even where this may appear convenient to do so. use separate vias to connect directly to the common ground plane. all supplies should be decoupled using surface mount 100nf to 1f capacitors, placed as close as possible to the device. for each pair of dvdd/dvss pins it is recommended that the capacitor is located on the reverse of the pcb, immediately under the device, with vias to the supply and ground planes as close as possible to the device and capacitor. this layout minimizes tracking, including the plated through hole, and hence keeps loop inductance to a minimum. see figure 19 (0603 size capacitors used). for the analog supplies, the decoupling scheme in figure 19 should be used. this scheme uses seven 0603 100nf capacitors. this allows the decoupling capacitors, that also need to be placed close to the device, to be fitted into a small area. deviation from the layout in figure 19 is not recommended as the device pinout has been carefully developed alongside this pcb design to give optimum performance. for single component-sided pcb designs all decoupling capacitors should be placed in a ring around the edge of the device as close as the assembly process will allow. the position of the capacitors should be such as to minimise the distance from the ball, and the tracking must run directly from the supply ball to the capacitor. positioning the decouplers close to the device is the highest priority layout consideration. of the analog decouplers, the vref to avss 100nf capacitor has the lowest priority (so is not shown in figure 19), however this decoupler should be positioned as close as reasonably practical to the device. tracking and vias should be excluded from the zone highlighted in figure 19(a). this recommendation is to maximise separation between lvds data bits in proximity of the analog outputs. the central array of thermal/ground balls should be connected directly to the ground plane. this array has two functions. firstly it connects the substrate to the ground plane that is most able to collect the noise from the mostly digital regions of the die. secondly, the thermal array is used to conduct heat directly out of the die and into the pcb ground plane for heat spreading. the design of the pcb around the thermal/ground array is critical for maximum heat transfer and ground plane integrity. a fujitsu design guide, ?pcb design rules for efbga packages?, document number fme/ms/apps/dg/4568, provides a detailed description of the recommended pcb design principles for this package.
october 2005 version 1.2 fme/ms/dac80/ds/4972 mb86064 dual 14-bit 1gsa/s dac copyright ? 2004-2005 fujitsu microelectronics europe gmbh production page 41 of 52 disclaimer : the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales repr esentatives before ordering.the information and circuit diagrams in this document are presented ?as is?, no license is grant ed by implication or otherwise. figure 19 recommended pcb layout (all plots viewed from above) a: top layer b: bottom layer c: internal layer 1 - ioutb tracks (thick) d: internal layer 2 - iout tracks (thick) up to the termination resistors and clkinb track (thin) clkin track (thin) iout and ioutb tracks from the termination resistor up to the termination resistors and iout termination resistors clkin termination analog decouplers (0603) pin 1 pin 1 pin 1 pin 1 see section 6.1
october 2005 version 1.2 fme/ms/dac80/ds/4972 mb86064 dual 14-bit 1gsa/s dac page 42 of 52 production copyright ? 2004-2005 fujitsu microelectronics europe gmbh disclaimer : the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales repr esentatives before ordering.the information and circuit diagrams in this document are presented ?as is?, no license is grant ed by implication or otherwise. 6.2 input clock interfacing the differential clock input to the device needs to be biased about the specified typical common mode input voltage. the exact interface circuitry will depend on the functionality required but an example is illustrated in figure 20. figure 20 clock input interfacing in most applications an external single-ended rf clock will not be used and a differential pecl clock could be connected directly to the ac-coupling capacitors. the above circuit utilises the on-chip regulated 1.8v supply, combined with the 1k/2k resistive divider, to generate a 1.2v common mode voltage. this could easily have been applied to the clock signals through higher value resistors, e.g. 4k7, in place of the 50r termination resistors. in this instance a 100r differential load should be added. where adjustment to the clock dc offset is required a trim-pot or trim-dac could be included as part of the 1k/2k potential divider circuit. adtl2-18 avss avd18_clk avss 1k 2k 50r 50r clkin clkinb 100nf dvss rf input clock
october 2005 version 1.2 fme/ms/dac80/ds/4972 mb86064 dual 14-bit 1gsa/s dac copyright ? 2004-2005 fujitsu microelectronics europe gmbh production page 43 of 52 disclaimer : the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales repr esentatives before ordering.the information and circuit diagrams in this document are presented ?as is?, no license is grant ed by implication or otherwise. 6.3 clock duty cycle optimisation earlier sections of this data sheet document that the dac core is clocked on both rising and falling edges of the input clock, and that a characteristic of this architecture is suppressed images of the generated signal relating to fclk. any duty cycle error in the input clock will exacerbate the fclk-fsig image. this can be minimised by using a filtered, sinusoidal clock and if necessary trimming the differential dc offset. applications using a square wave clock are unlikely to achieve the 50:50 duty cycle necessary to deliver best wide-band spurious performance. measurements and calculations show that for an output at 3/8fdac a duty cycle error of 1% (49:51) gives 32dbc rejection. in cases where maximal suppression of the fclk-fsig image is required it is recommended to either filter the clock or implement a tuned circuit as part of the clock routing. a band-pass filter can be used but a low-pass response allows for some variation in clock frequency to be accommodated. a key target of the filter is to suppress the second harmonic by 40db. this will reduce the duty cycle error by approximately 100 times, or in other words to a negligible level. for most applications a third order l-c filter should meet these requirements. it is important to ensure that the resultant clock amplitude meets the required specification otherwise phase noise will increase due to reduced slew rate. an alternative is to construct a tuned circuit by linking clk to clkb with two 50 ? delay lines, one at the clock source and the other at the dac. the delay time required is equivalent to one half of a clock period. the delay line links will need to be ac coupled from the clock source if a dc short is not supported. similarly, ac coupling with appropriate biassing, prior to the dac input, would be necessary where trimming of the differential dc offset is required. this approach has also demonstrated a reduction in duty cycle error by approximately 100 times. the two delay lines can be implemented in the pcb tracking. the length of tracking required depends on the pcb signal propagation speed. for example, a delay of 1.35ns would be used in system operating at a clock frequency of about 370mhz, and would be realised with a pcb track length of about 27cm, assuming 5ns/m propagation speed on the pcb. tracking the delay would be by zig-zagging backwards and forwards on a spare inner layer. the two delay lines must be separated by pcb tracks sufficiently long that a clock edge finishes exiting the first delay line before entering the second, i.e. td > tr, or spacing > 10cm for tr=0.5ns. figure 21 clock duty cycle optimisation using delay line links square wave clock source mb86064 clock input 1 st delay line link 2 nd delay line link
october 2005 version 1.2 fme/ms/dac80/ds/4972 mb86064 dual 14-bit 1gsa/s dac page 44 of 52 production copyright ? 2004-2005 fujitsu microelectronics europe gmbh disclaimer : the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales repr esentatives before ordering.the information and circuit diagrams in this document are presented ?as is?, no license is grant ed by implication or otherwise. 6.4 analog output interfacing 6.4.1 transformer coupled output circuit the recommended analog output circuit is a two stage transformer circuit that provides both isolation from the analog ground plane and excellent common-mode rejection, whilst providing the required differential to single-ended conversion. the recommended transformers are a mini-circuits (www.minicircuits.com) adtl1-4-75 transmission line transformer, and an adt1-1wt balun. see figure 22. for best performance the dac output expects to see a low impedance load. when considering the recommended circuit, it is important to note that transformer adt1-1wt is not exactly 1:1 turns ratio. instead, when a 50 ? load is attached to its secondary winding, a primary impedance of approx. 68 ? is exhibited. hence, each dac output sees 33 ? /34 ? in parallel with 34 ? , i.e. approx. 16.5 ? /17 ? . see figure 22. the primary load can either be two 33 ? precision resistors to ground or a bridged single 68 ? resistor. figure 22 recommended transformer coupled analog output circuit the primary load resistor(s) should be positioned as close as possible to the iout and ioutb balls, only second in layout priority to the analog decoupling capacitors. the tracking between the dac and the resistor(s) should be very closely coupled, ideally as a broadside coupled stacked differential pair positioned between two ground planes, with low (approx. 33 ? ) differential impedance tracking. where two single-ended load resistors are used these should be closely matched to maximise cmrr. the tracking from the termination resistors to the transformer should also be closely coupled, but now routed adjacent to a ground plane as an edge coupled differential pair for best impedance matching. special attention should be paid to the routing of these tracks. the tracks must always be routed as a matched pair and be equal in length. the routing of these tracks should avoid coming into close proximity to any power or signal tracks, plane edges or even vias that may cause more noise to be induced onto one of the tracks than the other. switching routing layers should be avoided, but if 33r 33r 33r 33r 10pf analog out adt1-1wt adtl 1-4-75 avss avss avss iout ioutb 50 ? 68r or
october 2005 version 1.2 fme/ms/dac80/ds/4972 mb86064 dual 14-bit 1gsa/s dac copyright ? 2004-2005 fujitsu microelectronics europe gmbh production page 45 of 52 disclaimer : the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales repr esentatives before ordering.the information and circuit diagrams in this document are presented ?as is?, no license is grant ed by implication or otherwise. necessary, the ground planes that the signals use as a reference plane must be linked together with vias next to the signal vias so that the return currents in the ground plane do not have to travel any distance away from the signal tracks when switching ground layers. the rcr network, shown in figure 22, is to compensate for the adt1-1wt transformer becoming inductive at high frequencies. the 10pf capacitor can be replaced with a variable capacitor to allow optimisation of overshoot at the transformer input. however, this may not be required in all instances, particularly frequency domain applications, since it increases in-band roll-off. for direct-if, bandpass applications it may be possible to tune out the dac?s output capacitance, cout, by resonating it with a parallel inductor. for example, about 16nh to gnd at each output or 33nh between the outputs for a ~270mhz if (assuming ideal resistive load). the adtl1-4-75 transmission line transformer may be removed to simplify the circuit, but this will reduce high frequency rejection of common-mode noise and may reduce system performance in some applications. for either higher impedance or dc coupled loads it is important to note that the output voltage compliance range for best performance is symmetrical about -0.3v not 0v. 6.4.2 direct interface to quadrature modulator some applications require a dc shift in order to interface the dac output directly to components such as a quadrature modulator. traditionally this is not an easy challenge without impacting noise and distortion. however, it may be possible to achieve the optimum operating point of both components by off-setting supply rails/domains. for example, consider a modulator that normally runs on a +5v supply and requires a +1.5v dc bias at its baseband inputs. whereas the optimum dc bias at the dac output (for maximum signal swing) is -0.3v. by shifting the modulator supply to operate between +3.3v (already needed for the dac) and -1.8v (at all gnd pins) supplies, providing a total and acceptable 5.1v supply, all that is needed is appropriate termination resistors at the dac output, split between 0v and -1.8v, to give the correct -0.3v dc bias at the dac output and meet the optimal +1.5v dc bias, relative to its vss pins, at the modulator input. figure 23 suggested direct interface to quadrature modulator 50r 50r 10r avss iout ioutb avss avd33 +3.3v 50r 50r -1.8v in_p in_n vss vdd -1.8v +3.3v mb86064 quadrature modulator avss -0.3v (dc) -0.3v (dc)
october 2005 version 1.2 fme/ms/dac80/ds/4972 mb86064 dual 14-bit 1gsa/s dac page 46 of 52 production copyright ? 2004-2005 fujitsu microelectronics europe gmbh disclaimer : the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales repr esentatives before ordering.the information and circuit diagrams in this document are presented ?as is?, no license is grant ed by implication or otherwise. 6.5 example setup register settings the following sections provide examples of typical configurations for the mb86064 and required register settings. in all cases other registers are assumed to be at their default values, following a device reset. 6.5.1 dual dac, lvds data, clock outputs enabled address data note ? 0x1b2 0x0000000 set recommended dac core delay settings 0x1c3 0x00001c0 power up device and enable clock outputs 6.5.2 single dac, lvds data port a, driving dac a address data note 0x1b2 0x0000000 set recommended dac core delay settings 0x1c0 0x0000002 set iref for dac a only configuration 0x1c3 0x0000bc0 power up dac a and enable clock outputs 6.5.3 multiplexed lvds data into dac a (a=even, b=odd) address data note 0x00 0x10 set wmm/lvds data mux to wmm 0x21 0x01 set odd mux0 = mux1 data 0x1b2 0x0000000 set recommended dac core delay settings 0x1c0 0x0000002 set iref for dac a only configuration 0x1c3 0x00009c0 power up data ports, dac a and clock outputs 0x1c4 0x0000080 enable wmm clock (bit #1 to ?0?) 6.5.4 waveform memory module, different a & b waveforms address data note 0x10 0x00 enable even memory 0x20 0x00 enable odd memory 0x1b2 0x0000000 set recommended dac core delay settings 0x1c3 0x00007e0 power up both dacs, disable lvds ports 0x1c4 0x0000081 enable wmm clock, disable clock outputs
october 2005 version 1.2 fme/ms/dac80/ds/4972 mb86064 dual 14-bit 1gsa/s dac copyright ? 2004-2005 fujitsu microelectronics europe gmbh production page 47 of 52 disclaimer : the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales repr esentatives before ordering.the information and circuit diagrams in this document are presented ?as is?, no license is grant ed by implication or otherwise. {load waveform data into memories, start addr=0 length=2047(0x7ff)} {this length corresponds to a vector length of 16k points} 0x13 0xxxxxxxx {write first data word} 0x12 0x27ff800 program ram controller: ram a, even, write 0x13 0xxxxxxxx {write next data word} {repeat above instruction 2045 times} 0x13 0xxxxxxxx {write last data word} 0x23 0xxxxxxxx {write first data word} 0x22 0x27ff800 program ram controller: ram a, odd, write 0x23 0xxxxxxxx {write next data word} {repeat above instruction 2045 times} 0x23 0xxxxxxxx {write last data word} {repeat for ram b} 0x12 0x07ff800 program ram controller: ram a, even, run 0x12 0x0fff800 program ram controller: ram b, even, run 0x22 0x07ff800 program ram controller: ram a, odd, run 0x22 0x0fff800 program ram controller: ram b, odd, run 0x11 0x33 set even mux0 = mux1 = ram data 0x21 0x33 set odd mux0 = mux1 = ram data 0x10 0x01 set software reset to sync rams 0x10 0x00 clear software reset to sync rams 0x00 0x10 set wmm/lvds data mux to wmm 6.6 technical support requests for technical support on the mb86064 may be e-mailed to: msd.support@fme.fujitsu.com
october 2005 version 1.2 fme/ms/dac80/ds/4972 mb86064 dual 14-bit 1gsa/s dac page 48 of 52 production copyright ? 2004-2005 fujitsu microelectronics europe gmbh disclaimer : the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales repr esentatives before ordering.the information and circuit diagrams in this document are presented ?as is?, no license is grant ed by implication or otherwise. 7 development kit a development kit, reference dk86064-2, is available for the mb86064 dual 14-bit 1gsa/s dac. this comprises an evaluation board for the mb86064 and a pc programming cable with associated software. connections for all analog signals are via sma connectors, allowing instruments to be connected using standard cables. all digital i/o signals are routed to four 2-row 0.1? headers, allowing the board to be connected to a suitably designed customer?s board if required. the dk86064-2 development kit includes, evaluation board with mb86064 device fitted usb programming cable for control of the dac from a host pc windows pc based control software shielded power supply cable user manual to convert the 2-row 0.1? data headers on to sma style connectors, an optional adaptor kit is available, dk86064-1-sma in addition to the complete development kit, key modules are available individually, dkusb-1 pc usb programming cable and control software for further assistance, including price and availability of the development kits, please contact your fujitsu sales representative.
october 2005 version 1.2 fme/ms/dac80/ds/4972 mb86064 dual 14-bit 1gsa/s dac copyright ? 2004-2005 fujitsu microelectronics europe gmbh production page 49 of 52 disclaimer : the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales repr esentatives before ordering.the information and circuit diagrams in this document are presented ?as is?, no license is grant ed by implication or otherwise. 7.1 using dkusb-1 in target applications it is expected that customers can benefit from using fujitsu?s pc usb programming cable and accompanying pc software, dkusb-1, for debug of prototype target applications. to facilitate this it is recommended that an appropriate connector is fitted to the target board, providing connections to the following signals as a minimum, dvdd (+1.8v) dvss serial_in serial_out serial_clk serial_en x_reset an interface cable will need to be assembled to connect from the board to the 10 x 2 row 0.1? header on the pc usb cable control box. figure 24 recommended application pc control interface connector this will allow full control of the mb86064 either prior to implementation of the target system dac controller or to assist with initial debug of the dac circuitry. full access to configuration registers as well as the wmm is possible. x_reset serial_in serial_out serial_clk serial_en mb86064 5 x 100r 1 2 19 20 15 17 13 dvdd dvss to target system dac controller, e.g. fpga pc control interface connector
october 2005 version 1.2 fme/ms/dac80/ds/4972 mb86064 dual 14-bit 1gsa/s dac page 50 of 52 production copyright ? 2004-2005 fujitsu microelectronics europe gmbh disclaimer : the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales repr esentatives before ordering.the information and circuit diagrams in this document are presented ?as is?, no license is grant ed by implication or otherwise. appendix a default register settings appendix a.1 dac core registers register address register bits 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 dac a 190 16 [7:0] thold 01 1001 0000 0 0 0 0 0 0 0 0 dac a 191 16 [27:21] [20:14] [13:7] [6:0] seed 01 1001 0001 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 dac b 1a0 16 [7:0] thold 01 1010 0000 0 0 0 0 0 0 0 0 dac b 1a1 16 [27:21] [20:14] [13:7] [6:0] seed 01 1010 0001 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 dac core 1b2 16 9 8[7:4] [3:0] clock delays 01 1011 0010 0 0 01000100 dac a & b 1b3 16 4 3 2 1 0 core 01 1011 0011 0 0 0 0 0 dac 1c0 16 210 config 01 1100 0000 x00 system clock 1c1 16 [15:12] [11:8] [7:4] [3:0] delays 01 1100 0001 0000000000000000 dac 1c2 16 [2:0] test 01 1100 0010 x 0 0 power 1c3 16 12 11 10 9876543210 down 01 1100 0011 1111111000000 system 1c4 16 7 [6:2] 1 0 misc 01 1100 0100 1 0 0 0 0 010 r read-only bit x don?t care not used reserved. set to defined value
october 2005 version 1.2 fme/ms/dac80/ds/4972 mb86064 dual 14-bit 1gsa/s dac copyright ? 2004-2005 fujitsu microelectronics europe gmbh production page 51 of 52 disclaimer : the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales repr esentatives before ordering.the information and circuit diagrams in this document are presented ?as is?, no license is grant ed by implication or otherwise. appendix a.2 waveform memory module registers register address register bits 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 wmm 00 16 7 6 5 4 [3:2] [1:0] config 000 0000 0 0 000000 wmm even 10 16 7 6 5 4 3 210 config 001 0000 0 0 0 r r 010 wmm even 11 16 [7:6] 5 4 [3:2] 1 0 mux ctrl 001 0001 00000000 wmm even 12 16 25 [24:23] 22 [21:11] [10:0] ram ctrl 001 0010 00001111111111100000000000 wmm even 13 16 63 62 61 60 59 note: 64 bit register 4 3 2 1 0 ram data 001 0011 wmm odd 20 16 7 6 5 4 3 210 config 010 0000 0 0 0 r r 010 wmm odd 21 16 [7:6] 5 4 [3:2] 1 0 mux ctrl 010 0001 00000000 wmm odd 22 16 25 [24:23] 22 [21:11] [10:0] ram ctrl 010 0010 00001111111111100000000000 wmm odd 23 16 63 62 61 60 59 note: 64 bit register 4 3 2 1 0 ram data 010 0011 r read-only bit x don?t care not used reserved. set to defined value
52 worldwide headquarters japan asia tel: +81 44 754 3753 fax: +81 44 754 3329 fujitsu limited kamikodanaka 4-1-1 nakahara-ku kawasaki-shi kanagawa-ken 211-8588 japan tel: +65 281 0770 fax: +65 281 0220 fujitsu microelectronics asia pte ltd 151 lorong chauan new tech park #05-08 singapore 556741 http://www.fujitsu.com http://www.fmal.fujitsu.com usa europe tel: +1 408 737 5600 fax: +1 408 737 5999 fujitsu microelectronics america, inc. 1250 e. arques avenue, m/s 333 sunnyvale, ca 94088-3470 usa t el: +49 6103 6900 fax: +49 6103 690122 fujitsu microelectronics europe gmbh am siebenstein 6-10 d-63303 dreieich-buchschlag germany tel: +1 800 866 8608 fax: +1 408 737 5984 customer response center mon-fri: 7am-5pm (pst) http://www.fma.fujitsu.com/ http://emea.fujitsu.com/microelectronics october 2005 version 1.2 fme/ms/dac80/ds/4972 mb86064 dual 14-bit 1gsa/s dac page 52 of 52 production copyright ? 2004-2005 fujitsu microelectronics europe gmbh disclaimer : the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales repr esentatives before ordering.the information and circuit diagrams in this document are presented ?as is?, no license is grant ed by implication or otherwise. fme/ms/dac80/ds/4972 1.2 the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information and circuit diagrams in this document presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. also, fujitsu is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. no license is granted by implication or otherwise under any patent or patent rights of fujitsu microelectronics europe gmbh. fujitsu semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). caution: customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (suc h as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, e tc.) are requested to consult with fujitsu sales representatives before such use. the company will not be responsible for damages arising from such use without prior approval. any semiconductor devices have inherently a certain rate of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prev ention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade control law of japan, the prior authorization by japanese government should be required for export of those products from japan.

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